As memory device density increases, inter-bit line space decreases. For high density integration, inter-bit line capacitance is higher than the bit line and fringe capacitance. Thus, capacitive bit line-to-bit line coupling is of serious concern.
FIG. 1 shows a burst mask ROM capable of reading out serial data. Referring to FIG. 1, the ROM device includes an array of memory cells 12 (the individual memory cells are not shown) disposed in a matrix of rows and columns and a plurality of bit lines BLi, where i=1 to 64. The bit lines BLi are selected by the 16-bit column selection signals YA0 to YA7 and YB0 to YB7. The memory cell array 12 is divided into 8 memory cell blocks 12-1 to 12-8, each having 8 bit lines. The ROM device, as is well known, can be a NAND-type or a NOR type depending upon the layout of memory cells. Generally, a NAND-type ROM has a smaller-sized memory cell array than a NOR-type ROM. The memory device shown in FIG. 1 further includes a bit line discharge circuit 14, a bit line charge circuit 16, a precharge level detecting circuit 18, a data sensing circuit 20, column selection circuits 22 and 24, and a data output circuit 26.
The memory device according to this embodiment typically includes a column predecoder circuit (not shown) and a data read out control circuit (not shown) disposed in close proximity to the memory cell array 12. The column decoder circuit and data read out control circuit are well known and are not described in further detail.
In addition to the memory cell array 12, each of the following associated circuits is divided into 8 blocks which correspond to the memory cell blocks 12-1 to 12-8, respectively: the bit line discharge circuit 14 (14-1 to 14-8), the bit line charge circuit 16 (16-1 to 16-8), the precharge level detecting circuit 18 (18-1 to 18-8), the data sensing circuit 20 (20-1 to 20-8), and the column selection circuit 22 (22-1 to 22-8). For instance, bit line discharge block 14-1, bit line charge block 16-1, precharge level detecting block 18-1, data sensing block 20-1, and column selection block 22-1 are formed in close proximity to memory cell block 12-1. Each of the bit line discharge circuit blocks 14-1 to 14-8 and each of the precharge level detecting circuit blocks 18-1 to 18-8 is formed by 8 NMOS transistors. Each of the bit line charge circuit blocks 16-1 to 16-8, data sensing circuit blocks 20-1 to 20-8, and column selecting circuit blocks 22-1 to 22-8 is formed by 8 PMOS transistors.
A discharge control signal Pdis is applied to the gates of the NMOS transistors included in the bit line discharge circuit 14. A precharge control signal Pbpre is also provided to the gates of the PMOS transistors included in the bit line charge circuit 16. The gates of the NMOS transistors included in the precharge level detecting circuit 18 are supplied with a precharge level control signal Vbias.
For each column selection block 22-1 to 22-8, the column selection signals YA0 to YA7 are applied to the gates of the PMOS transistors included therein. The gates of the 8 PMOS transistors included in the column selection circuit 24 are controlled by the column selection signals YB0 to YB7. The transistors of the column selection circuit 24 corresponds to the column selection blocks 22-1 to 22-8, respectively. The drains of the PMOS transistors included in the column selection circuit 24 are commonly connected to a data line DL. The data output circuit 26 comprises an NMOS transistor 27 and a NAND gate 28. The gate of the NMOS transistor 27 is provided with a control signal Siref from a read out control circuit (not shown) and its source-drain channel is connected between the data line DL and the ground voltage Vss. The read out control circuit is well known and will not be discussed in further detail. The NAND gate 28 has a first input for receiving the data signal on the data line DL, a second input for receiving a control signal SAfc from the read out control circuit (not shown), and an output for outputting a valid data signal PLj, where j=0 to 7.
FIG. 2A is an exemplary circuit for generating the precharge control voltage Pbpre shown in FIG. 1. Referring to FIG. 2A, the precharge control voltage generation circuit includes PMOS transistors 30, 34, and 36, inverters 32, 42, and 48, a NAND gate 44, and NMOS transistors 40, 50, and 52.
A control signal PRE from the data read out control circuit is applied to the gate of the PMOS transistor 30. Inverters 32 and 42 receive control signals STB and PRE, respectively, from the data read out control circuit. The control signal Vref generated by the data read out control circuit is applied to the gate of the NMOS transistor 40. The gate of the NMOS transistor 52 is supplied with the control signal PRE.
FIG. 2B is an exemplary circuit for generating the precharge level control voltage Vbias shown in FIG. 1. Referring to FIG. 2B, the precharge level control voltage generation circuit includes an inverter 54, a differential amplifier section 56, a pull-up transistor 64, a voltage divider section 66, and a pull-down transistor 68.
The differential amplifier section 56 has a first input terminal 58 for receiving the control signal Vref generated by the data read out control circuit, a second input terminal 60 coupled to the voltage divider section 56, and an output terminal 62 coupled to the gate of the pull-up transistor 64. The gates of transistors 76 and 80 are commonly supplied with the control signal Vref. The gate of transistor 78 is coupled to the voltage divider section 67. The control signal STB is provided to gates of transistors 68 and 82 via the inverter 54.
The voltage divider section 66 includes two serially connected resistors 84 and 86 for providing the control signal Vbias with different voltage levels responsive to the control signal Vref. The junction of the resistors 84 and 86 is connected to the input 60 of the differential amplifier section 56.
FIG. 3 is a timing diagram for the read operation of the semiconductor memory device shown in FIG. 1. The data read operation of the conventional ROM device will be described with reference to FIG. 3 and FIGS. 1, 2A, and 2B.
During the stand-by period T1, the control signal Pdis is set to the power supply voltage Vcc (e.g., 3.3 volts or 5 volts) such that all of the bit lines BLi are discharged and set to a ground voltage Vss by the discharge circuit 14. Also, the control signals STB and Vref are set to the power supply voltage Vcc while the control signal PRE is set to ground voltage Vss. Thus, the PMOS transistors 30, 34, 36, shown in FIG. 2A, are activated and the NMOS transistors 50 and 52, also shown in FIG. 2A, are deactivated resulting in the precharge control signal Pbpre changing to a power supply voltage Vcc. In the precharge level control voltage generating circuit shown in FIG. 2B, the precharge level control voltage Vbias changes to the power supply voltage Vcc by the action of the pull-up transistor 64 because NMOS transistors 82 and 68 are deactivated. Therefore, the voltage levels of nodes N1 to N64 between the bit line charge circuit 16 and the data sensing circuit 20 are equal to those of the bit lines BL1 to BL64.
During the bit line precharge period T2, control signal STB and discharge control signal Pdis are pulled down to ground voltage Vss, control signal PRE changes to power supply voltage Vcc, and control signal Vref changes to a predetermined voltage level V.sub.REF1 (e.g., 1.2 volts). Thus, the discharge circuit 14 shuts off preventing the bit lines BLi from further discharging. During the precharge period T2, the precharge control signal Pbpre changes to a ground voltage Vss and precharge level control voltage Vbias changes to a predetermined voltage level V.sub.REF2 (e.g., 2 volts). By doing so, the PMOS transistors included in the bit line charge circuit 16 are turned on so that source currents flow to the bit lines BLi from the power supply voltage Vcc.
During the bit line precharge period T2, the differential amplifier section 56 is activated since the control signal STB is pulled down to ground voltage Vss. The output voltage of the amplifier section 56 depends on the input voltage applied its input terminal 60 because the control signal Vref applied to the input terminal 58 of the differential amplifier section 56 is constant and equal to V.sub.REF1. Thus, the voltage level V.sub.REF2 of the precharge level control signal Vbias is determined by the ratio of the on-resistance of the PMOS transistor 64 and the total resistance of the voltage divider section 66.
As described above, the precharge control signal Pbpre and the precharge level control voltage Vbias are pulled down to ground voltage Vss and reference voltage V.sub.REF2, respectively. The nodes N1 to N64 between the bit line charge circuit 16 and the data sensing circuit 20 are developed to power supply voltage Vcc. However, if the bit lines BL1 to BL64 reach the reference voltage V.sub.REF2 -Vtn, where Vtn is the threshold voltage of each NMOS transistor in the precharge level detecting circuit 18 the transistors included in the circuit 18 are turned off so that the charging operation of the bit lines stops. Consequently, all the bit lines are precharged to V.sub.REF2 -Vtn. Also, during the period T2, the control signal Siref changes to predetermined voltage level V.sub.REF3 which allows the data line DL to become higher than the trip voltage of the NAND gate 28 when at least one of the nodes Ni (i=1 to 64) changes to ground voltage Vss, that is, when logic high data is transferred to the data line DL via column selection circuits 22 and 24. The NAND gate 28 outputs valid data PLj, where j=0 to 7, only when the control signal SAfc is at a logic high level (e.g., at power supply voltage Vcc).
During the data sensing period T3, the control signal PRE changes to ground voltage Vss again while the control signal STB and the reference voltage Vref remain in the same state as in the bit line precharge period T2. Therefore, transistors 30, 36, 40, 50, and 52 shown in FIG. 2A are activated such that the precharge control signal Pbpre is pulled up to reference voltage V.sub.REF4 from ground voltage Vss. The reference voltage V.sub.REF4 makes about half of the on-cell current flow to each bit line from the charge circuit 16. During the data sensing period T3, where the selected memory cells are on-cells, i.e., cells having a current sink path, the corresponding bit lines BLi change to a voltage lower than V.sub.REF2 -Vtn. The corresponding nodes Ni are developed to the same levels as the corresponding bit lines. Where the selected memory cells are off-cells, i.e., cells having no current sink path, the bit lines and the nodes are maintained to the power supply voltage Vcc.
During the data output period T4, the control signal SAfc changes to power supply voltage Vcc and the sensed parallel data is serially provided by means of the column selection circuits 22 and 24 and the data output circuit 26.
In the data read scheme described above, a first and a second adjacent bit lines are connected to an on-cell and an off-cell, respectively. The off-cell bit line level falls for a short period of time because of the bit line-to-bit line coupling when the on-cell bit line is pulled down to ground voltage Vss as shown in FIG. 3. The slight downward change in the voltage level of the off-cell bit line causes the corresponding transistor of the bit line level detecting circuit 18 to turn on. The corresponding sensing node level also falls for a short time along with the off-cell bit line level until the on-cell bit line settles into a stable state. This capacitive coupling results in sensing time delays, sensing failures, and the like.